Basically, a DRAM is an integrated circuit that stores data in binary form (e.g., “1” or “0”) in a large number of cells. The data is stored in a cell as a charge on a capacitor located within the cell. Typically, a high logic level is in general equal to the power supply voltage and a low logic level is in general equal to ground.
The cells of a conventional DRAM are arranged in an array so that individual cells can be addressed and accessed. The array can be thought of as rows and columns of cells. Each row includes a word line that interconnects cells on the row with a common control signal. Similarly, each column includes a bit line that is coupled to at most one cell in each row. Thus, the word and bit lines can be controlled so as to individually access each cell of the array.
To read data out of a cell, the capacitor of a cell is accessed by selecting the word line associated with the cell. A complementary bit line that is paired with the bit line for the selected cell is equilibrated to an equilibrium voltage. This equilibration voltage (Veq) is typically midway between the high Vdd and low Vss (typically ground) logic levels. Thus, conventionally, the bit lines are equilibrated to one-half of the power supply voltage, Vdd/2. When the word line is activated for the selected cell, the capacitor of the selected cell discharges the stored voltage onto the bit line, thus changing the voltage on the bit line. A differential amplifier, conventionally referred to as a sense amplifier, is then used to detect and amplify the difference in voltage on the pair of bit lines.
FIG. 1 shows a conventional sense amplifier circuit which comprises ten transistors T1-T10 fabricated in bulk silicon CMOS technology. The sense amplifier comprises a pair of cross-coupled inverters arranged between the first bit line BL and the second bit line /BL complementary to the first bit line:                a first CMOS inverter having an output connected to the bit line BL and an input connected to the complementary bit line /BL,        a second CMOS inverter having an output connected to the complementary bit line /BL and an input connected to the bit line BL.        
Each CMOS inverter comprises:                a pull-up transistor T1, T2 having a drain and a source, and        a pull-down transistor T3, T4 having a drain and a source,        
the pull-up transistor T1, T2 and the pull-down transistor T3, T4 of each CMOS inverter having a common drain.
The sources of the pull-down transistors T3, T4 are connected to a foot switch transistor T5, which is itself connected to a pull-down voltage source providing a low supply voltage VL usually at a low voltage level VBLL referred to as ground GND, and controlled by a foot switch control signal “Sense”. The ground level of the low supply voltage VLsupply is used as a reference for the other voltage levels in the sense amplifier. In the circuit illustrated by FIG. 1, the foot switch transistor T40 is an N-MOS transistor. When the foot switch control signal “Sense” is high, the foot switch transistor T5 is conducting, and the ground voltage is transmitted to the common source node of the pull-down transistors T3, T4. When the foot switch control signal “Sense” is low, the foot switch transistor T5 is blocked and the common source node of the pull-down transistors T3, T4 is not pulled down.
The sources of the pull-up transistors T21, T22 are connected to a pull-up voltage source providing a high supply voltage VH usually at a high voltage level such as VDD.
The sense amplifier further comprises an equalization transistor T6 having its source/drain terminals respectively coupled to one of bit lines BL, /BL and having its gate controlled by an equalization control signal. The equalization transistor T50 of the circuit illustrated in FIG. 1 is an N-MOS type transistor.
The sense amplifier further comprises a pair of dedicated precharge transistors T7, T8 respectively coupled to the bit line BL and to the complementary bit line /BL and arranged to precharge the bit lines BL, /BL to a precharge voltage, usually at the mean value between the high supply voltage VH and the low supply voltage VL. This mean value is usually half the high supply voltage VHsupply high value, i.e. VH/2, since the low voltage level GND of the low supply voltage VL is used as a reference for the other voltages and the high supply voltage VH and low supply voltage VLS are usually then at their high and low voltage level, respectively. A precharge control signal ρPCH is applied to the gates of said precharge transistors T61, T62.
The sense amplifier further comprises two dedicated decode transistors T9, T10, the gates of which are controlled by a decoding control signal CSL. Each of the decode transistors T9, T10 connects one of the bit lines BL, /BL to a global bit line IO, /IO, also called in-out line. The decode transistors T9, T10 are used to transfer data between the bit lines BL, /BL and the global bit lines IO, /IO.
Although sense amplifiers are technically necessary, from an economical point of view the sense amplifiers can be considered as service circuits of the memory array and therefore as overhead that increases the area of the entire circuit and thus also its cost of fabrication.
Therefore, continuous efforts are made to minimize the area consumption of such sense amplifiers.